The present invention relates to a fabrication method of a semiconductor device, and more particularly to a dual polysilicon gate of a semiconductor device having a three-dimensional multi-plane channel and a fabrication method thereof.
With the increase in the scale of integration of a semiconductor device, there is a need for a sub-100 nm memory array transistor. The sub-100 nm transistor has very low threshold voltage due to the short channel effect, and thus the retention time is drastically decreased.
To solve the above limitation, a recessed channel array transistor (RCAT) has been developed. This RCAT has a long retention time because the channel length is longer than that of a typical planar type transistor.
In recent years, a dual polysilicon gate (DPG) process is being used for improving on/off-current characteristics (Ion/Ioff) of a logic device as well as retention characteristics from those of the RCAT. Particularly, in a device having a 3-dimensional memory cell transistor such as an RCAT, when employing a typical dual ion implantation where phosphorous (P) and boron (B) ions are implanted into NMOS and PMOS transistors, respectively, the doping concentration in the polysilicon under the recessed channel is too small, and this fact causes polysilicon depletion to occur. Therefore, the DPG process is used so that polysilicon doped with low concentration phosphorous is deposited, and thereafter boron ions with very high dose (e.g., beyond 1E16/cm2) are implanted into the PMOS region. Herein, such an implantation is so called a converted DPG or a counter doping.
FIGS. 1A to 1C illustrate a typical method of forming a dual polysilicon gate.
Referring to FIG. 1A, a device isolation structure 12 is formed in a substrate 11 where a cell array region and a peripheral circuit region are defined. Here, the peripheral circuit region includes a peripheral NMOS region and a peripheral PMOS region. A hard mask layer is formed on the resultant structure, and patterned to form a hard mask pattern 13 defining a recessed channel region in the cell array region. The substrate 11 of the cell array region is etched using the hard mask pattern 13 as an etch barrier to thereby form a recessed channel region 14 in a trench shape.
Referring to FIG. 1B, the hard mask pattern 13 is removed. After forming a gate insulating layer 15 on the resultant structure, a phosphorous-doped N+ polysilicon layer 16A is deposited on the gate insulating layer 15 until it fills the recessed channel region 14. A photoresist layer 17 is formed covering the cell array region and the peripheral NMOS region. Boron (B) ions 18 are implanted into the N+ polysilicon layer 16A of the exposed peripheral PMOS region to form a P+ polysilicon layer 16B.
Referring to FIG. 1C, after the photoresist layer 17 is removed, a high-temperature thermal treatment 19 is performed to form the phosphorous-doped N+ polysilicon layer 16A in the cell array region and the peripheral NMOS region, and form the boron-doped P+ polysilicon layer 16B in the peripheral PMOS region. However, when doping boron ions according to the typical method, a very high dose boron ion implantation is required (e.g., beyond 1E16/cm2) because the heavily doped P+ polysilicon layer 16B should be formed by implanting boron ions into the phosphorous-doped N+ polysilicon layer 16A.
When forming the P+ polysilicon layer 16B by implanting high-dose boron ions, the curing of the photoresist layer 17 used in the ion implantation is intensified. As a result, it is difficult to strip the photoresist layer in a following process. Accordingly, this difficulty causes residue from the photoresist layer to remain even after the cleaning process, and on top of that the residue reacts with the metallic material deposited on the polysilicon layer.